Nixie Clock: High Voltage Converter

Posted

2026-09-15

Series

Part 2 of N, ongoing

This post will cover the design of the clock's high voltage converter, which takes 5-12V DC in and provides 3W at approximately 170V. We'll look at the basic design principles I followed, work through the design piece by piece and talk about some of the issues I've encountered, design choices that have made my life harder, and issues I haven't figured out yet.

In case you didn't come here from the previous post, a quick reminder that the full design is available on GitHub:

Choosing the Topology

Basically at some point I came across the Coilcraft transformers and thought they would look cool on a board. Thus the design topology was set from the beginning as a flyback. It doesn't hurt that "flyback" is a way cooler name than "boost". After the fact. Looking at the next revision, I did some checking that suggested a flyback could be more efficient at 5 V input.

I started out years ago looking at the Coilcraft design guidelines for the DA2032-AL, which point to a specific chip, the LT3750. But that chip is a capacitor charging chip, not suitable for continuous DC/DC conversion, so I got kind of stuck down a rabbit hole and set the project aside for a while.

After the conversation mentioned in the overview, I decided to take another look this time I had also been exploring the capabilities of LLMs in some other projects so I decided to ask it. That lead to a process of research where the LLM would give me something, I would go download and read some datasheets, have the LLM read the datasheets and help me with details I didn't understand, which ended up creating a nice cycle that kept me engaged and making progress from that day some time in late July/early August to at least now as I write this post in mid-September.

After picking the DA2032-AL, some back and forth with the LLM pretty quickly settled on the TI LM5156HChanged at the last minute to a LM51561H, which is the exact same chip with hardware hiccup protection, a likely mistake I'll talk about below. controller to drive the converter. I really think there's a part that would work here from most of the major chip manufacturers, just something about TI's datasheets works for me.

The final major design decision was to support 5-12V in. I started with a standard 12V barrel jack in mind, quickly decided that USB Power Delivery would be more convenient, expanded the range to 9-12V "for compatibility"It turns out that every USB-PD charger I have access to offers 12V even though it is not a required voltage under version 2 of the USB-PD spec, while at the same time the final design has a nearly flat efficiency curve across the full input range according to the design analysis I did., and finally about half way through the design process dropping the lower end to 5V in hopes of being able to run the clock from a computer port. In hindsight, I don't think there was really any reason to keep 12V. Designing for a pure 5V input would have given me a lot more margin in important areas and I have yet to find a 5V only USB-C port that won't run the clock.

Key features

• The turns ratio of the transformer directly sets the reflected voltage in a flyback converter. 1:10 keeps the reflected voltage down around 17V. At 1:5 the reflected voltage would double, significantly impacting component selection on the low voltage switching side. Conversely 1:20 would halve the reflected voltage, but as far as I can tell no suitable part with a higher than 1:10 ratio exists.

• Discontinuous Conduction Mode (DCM) operation significantly simplifies control-loop operation by allowing the secondary current to reach zero before the next switching cycle begins. The tradeoff is higher peak current for the same output power.TI has an excellent series of guides on flyback converter design, including one the covers DCM flyback design. Unfortunately I just discovered this right now, as I am writing this article.

• No isolation: One of the features a transformer offers is ground isolation between the high side and the low side. The is not possible in this design because the K155D1 drivers use a single common ground for both their logic inputs and the tube cathode currents.

Key sub-components in detail

The following sections will walk through some sections of the schematic in detail, these sections cover everything in the full schematic that does not come more or less straight out of the LM5156H datasheet's reference design.

Gate Drive and the Bias Charge Pump

This came up fairly late in the design for me because I did most of the design work based on 9-12V, but I find the 5V operation mode to be far more interesting now that I've proven it works, and gate drive is a key challenge to making that work.

Potentially the most substantial hurdle to 5V operation is that the LM5156H wants at least 8V on the BIAS pin to give the gate on the switching FET a strong drive. Below that, the gate drive rail may sag, which increases turn-off overlap, which is the largest loss term in our efficiency calculation. A convenient feature of the flyback topology is that we can attach the charge pumpQuoting Analog: A charge pump is "a type of dc-dc voltage converter that uses capacitors rather than inductors or transformers to store and transfer energy". in Fig. 2 to the switch node and harness the reflected voltage on the off time to create a high voltage source for BIAS.

The bias source does have a bit of a chicken and egg situation to resolve though. The charge pump only starts working once the converter is running, which requires the LM5156H to be powered. To solve this, we add a diode from the bus voltage rail (D5 in the figure) to give the chip a ~4.3V startup voltage. This substantially under-drives the FET, but it gets things going and the pump very quickly brings the voltage up.

This section of the design was the source of the only major part selection failure on the board. D4 was originally set as a ZPD3B0, which DigiKeyIf there's a way to report issues like this, I'd like to know lists as a 30V Zener. This is a typo in the database; that diode is actually 3V rather than 30V, so when I first plugged in the board bias was sitting way below the target. The LLM tried to warn me about this, but its phrasing wasn't very good and the right part number is so close that my skim of the datasheet didn't pick up the issue. Fortunately, this diode serves as a backup to clamp the max voltage on the bias input, so simply removing it let me continue testing until I eventually replaced it with a properly sized 30V diode.

Converter Enable and UVLO

The LM5156H uses a single input pin for UVLO (undervoltage-lockout) and enable logic. That pin allows switching once the voltage on it rises above 1.5V. The UVLO component of our circuit is almost trivial. It consists of R6 and R7 in Fig. 3, which form a voltage divider network to set the nominal UVLO turn-on threshold to 4.44V on V_BUS.

The remainder of the circuit implements the logic to allow the MCU to independently enable or disable the converter. The MCU needs to own this because V_BUS only supplies 500mA of current at startup. The MCU needs to first successfully re-negotiate a higher current limit, and only then allow the HV converter to turn on.

R2 and R17 bias Q2 on from V_BUS, so Q2 holds EN/UVLO low by defaultQ2, R2, and R17 are chosen such that Q2 holds EN/UVLO low well before V_BUS reaches the 4.44V turn-on threshold.. Driving EN_HV high turns Q3 on, which pulls Q2's gate low. Q2 then turns off, allowing the R6/R7 divider to control EN/UVLO. Biasing Q2 from V_BUS makes this default state independent of the MCU's power supply.

The pulldown on Q3's gate ensures that Q3 stays off when the MCU pin is high impedance. This is particularly important because the MCU is on an entirely different board, so may not even be present if someone manages to put a voltage on V_BUS without connecting this board to the main board.

This section of the design has worked well so far. The only thing that slightly concerns me is that it lacks redundancy. If either R2 or Q2 fails open, the circuit becomes permanently enabled. Q3 failing short would do the same. I'm undecided on whether these failure modes are likely enough to warrant fixing.

The RCD Clamp

At switch turn-off, the primary leakage inductance still carries peak current. Without the clamp, that current charges parasitic capacitances and drives V_SW sharply upward. The clamp limits the voltage stress on the switching FET.

D2 allows current to flow from V_SW into the clamp and blocks reverse current. C3 stores the energy from the pulse, and R3 dissipates it as heat.Once again, I will direct you to TI for a complete explanation of this. Returning the clamp to V_BUS closes the current path through the primary winding and the clamp. A ground return would include the input supply in that path, adding supply energy to the energy the clamp must dissipate.

Running the Clock

Initial Bring-up

As we'll discuss in the next post, the first startup of the main board went basically flawlessly. After that initial success I plugged in the HV board and powered up on a 5V supply just the main and HV boards with no clock face attached. A DMMI can't mention a DMM on this board without pointing out that it is a very bad idea to probe anything on this board with two hands. This isn't an OSHA training video, but if you don't know what you're doing, go look up how to deal with high voltages safely. This board definitely has the right conditions to kill you if handled irresponsibly. on the test points showed 170V on the first startup. Not quite so easy though; not wanting to risk the tubes quite yet, I made up a 15kΩ resistor string that I soldered into the test points, and immediately the converter failed to start up.

The LLM and I worked through possible causes and what I could test without a scope. One hypothesis was that charging the output capacitor while supplying the test load kept the converter in current limit long enough to trigger hiccup protection. I replaced the 470nF soft-start capacitor with 2.2µF to give the output nearly five times as long to rise. I think this was mostly a red herring. I still didn't have a satisfying explanation for the failed starts.

Connecting the face board at least gave me the brief satisfaction of seeing the tubes light for a fraction of a second, before they went dark again. To separate the converter's startup from the load of striking the tubes, I changed the firmware to let the HV rail stabilize first, then staggered ignition by 100ms. The result was consistent: any three tubes worked, in any three sockets I tried. Lighting the fourth caused the rail to fail.

The USB-PD current request was another possible constraint. My calculations indicated that 1.25A at 5V should be sufficient, but I increased the request to 2A to test whether that budget was limiting operation. Finally, all fourI had IN-12s laying around from the last aborted attempt at this project, but I had to order the INS-1s and they hadn't arrived yet. tubes ran reliably on 5V. That was encouraging... until I plugged in the second HV board I had built.

Reducing the output-voltage setpoint to around 163V lowered the total power the converter had to supply and got both boards running reliably on 5V. The INS-1 colon tubes arrived later, and both boards also worked with all six tubes installed. I finally had a working clock, including the 5V operation I had added three quarters of the way through the design. The 12V case remained frustratingly inconsistent.

12V Debugging

At this point we have a working 5V clock, and on 12V input it has worked occasionally, but not reliably. I took a little break from debugging to develop a command and telemetry system and a desktop client so that I could read the firmware logs while plugged in to 12V, which we'll talk about later. Unfortunately those logs didn't identify any cause of the failures.Although through a long series of plugging and re-plugging to test behavior, I did notice that the MCU was running fast enough to transmit log messages about losing power, presumably after I had pulled the plug. Apparently the bulk capacitors held enough charge for the clock to send a couple of log messages complaining about losing power after I had pulled the plug. For a while, a software reset after the initial failure would bring the clock up normally. Then that stopped working too, and I never established why.

I then tested startup at different output-voltage set-points on both boards. Through this testing I was able to establish that the board I had been using for most of the testing would run at 12V, but only with the voltage turned down to ~159.8V, leaves some of the digits below their specified operating current. The second board, at 162.9V is barely within spec, but only just, and I haven't run it enough to see whether it really holds.

Several different 12V adapters produced the same limits. Our loss calculations predicted much less difference between 5V and 12V operation. That's where the board sits today. The next best guess the LLM has that I can't immediately disprove is that switching noise on the current-sense input is triggering current limiting prematurely. I also believe the converter needs more power margin.

Next Rev Changes

Three main things I am considering for the next revision:

1. Increased capacity. Some quick calculations suggest that the GA3459-BL, while bigger and pricier, would give the converter about 30% more output capacity With the same basic circuit and component values adjusted for the higher current.
2. Make it SMD on the main board. I think this might clean up some of the potential noise sources. As part of that, I'd look for a switching FET with lower gate-drain charge, which the LLM suggested as a way to reduce switching losses. My original idea of an exposed retro-ish board that matches the nixie tube era seems unworkable when it's carrying 170V, so there's really no reason not to put it on the main board.
3. More test points. I did briefly borrow a scope and probe a few things, but the setup process was so tedious that I didn't do nearly as much as I should have.
4. Drop hiccup protection. I suspect that switching the LM51561H back to a LM5156H, dropping hiccup protection, would let the clock run. Even if it doesn't, I think it would make it easier to scope and debug. The LM5156H retains hardware peak-current limiting and firmware monitoring and control based on the chip's PGOOD output should provide sufficient safety.